r/intel • • 1d ago

News BIOSTAR announces Panther Lake-H Thin Mini-ITX motherboard with up to 128GB DDR5

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videocardz.com
52 Upvotes

r/intel • • 1d ago

News FEVM shows 2cm thin mini PC with Panther Lake and 64GB LPDDR5X-9600

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videocardz.com
18 Upvotes

r/intel • • 1d ago

News Intel takes massive chunk out of AMD's desktop CPU market share in unexpected turnaround - may be due to the red team's dominance in gaming chips, weirdly

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pcgamer.com
362 Upvotes

r/intel • • 2d ago

News Intel Core Ultra 7 260K launches as Newegg-exclusive CPU, now available in prebuilt gaming PCs

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videocardz.com
69 Upvotes

r/intel • • 2d ago

Information Intel adds Razor Lake desktop and laptop CPUs to its ISA reference

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videocardz.com
41 Upvotes

r/intel • • 3d ago

Discussion Has anyone compared NPU vs Arc iGPU vs CPU on the same OpenVINO task? (Meteor Lake)

14 Upvotes

The NPU in the Core Ultra 9 185H is rated at up to 11 TOPS, well under the 40 TOPS Microsoft requires for Copilot+, so it isn't a Copilot+ chip. Intel's OpenVINO plugins for Audacity (noise suppression, Whisper transcription, stem separation) can target the NPU as well as the CPU and GPU, so in theory you can run the same job on all three.

The usual NPU pitch is efficiency, which makes sense on a laptop battery. A plugged-in mini PC like the geekom it13 max (185H, Arc iGPU and an NPU) has no battery to save, so the case for the NPU comes down to power draw, heat and fan noise on longer jobs versus just letting the Arc iGPU finish faster.

Has anyone compared the same supported OpenVINO workload across the NPU, Arc iGPU, and CPU? I'm especially interested in execution time and measured power use, along with the model and backend used.


r/intel • • 4d ago

News Intel Releases New CPU Microcode To Fix A Variety Of Functional Issues

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phoronix.com
50 Upvotes

r/intel • • 4d ago

Information Intel's Next-Gen Diamond Rapids "Xeon 7" CPU Smiles For The Camera, A 256 P-Core Chip Built On 18A-P That Aims For A 2027 Launch

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wccftech.com
101 Upvotes

r/intel • • 5d ago

Discussion Optimizing a Reduction Algorithm with AVX

21 Upvotes

An example of optimizing a reduction algorithm using AVX-512 compiler intrinsics and std::experimental::native_simd types.

https://github.com/AndrewOfC/vector_reduction

The speedup is evaluated against a trivial implementation:

template<typename T>
T generic_reduction(T *src, size_t len, T initial)
{
    for(size_t i = 0; i < len; i++)
    {
        initial += src[i];
    }
    return initial;
}

And against the C++ standard library std::reduce.

Three approaches are used, but yield similar results in the 'sweet spot' between 1000 and 6000 samples.

Intrinsics and the stdx:native_simd have the same basic structure of:

NOTE: some blocks are not shown for the sake of brevity; full code is in the public GitHub repo.

while( len >= 8 * 8 ) {
    __m512d r000 = _mm512_load_pd(&src[0]);
    __m512d r001 = _mm512_load_pd(&src[8]);
    __m512d r002 = _mm512_load_pd(&src[16]);
    __m512d r003 = _mm512_load_pd(&src[24]);
    __m512d r004 = _mm512_load_pd(&src[32]);
    __m512d r005 = _mm512_load_pd(&src[40]);
    __m512d r006 = _mm512_load_pd(&src[48]);
    __m512d r007 = _mm512_load_pd(&src[56]);
    
    r000 = _mm512_add_pd(r000, r004);
    r001 = _mm512_add_pd(r001, r005);
    r002 = _mm512_add_pd(r002, r006);
    r003 = _mm512_add_pd(r003, r007);
    
    r000 = _mm512_add_pd(r000, r002);
    r001 = _mm512_add_pd(r001, r003);
    
    r000 = _mm512_add_pd(r000, r001);

    initial += _mm512_reduce_add_pd(r000) ;
    

    len -= 8 * 8 ;
    src += 8 * 8  ;
} 
// while
/*
 * 
 */
while( len >= 4 * 8 ) {
    __m512d r000 = _mm512_load_pd(&src[0]);
    __m512d r001 = _mm512_load_pd(&src[8]);
    __m512d r002 = _mm512_load_pd(&src[16]);
    __m512d r003 = _mm512_load_pd(&src[24]);
    
    r000 = _mm512_add_pd(r000, r002);
    r001 = _mm512_add_pd(r001, r003);
    
    r000 = _mm512_add_pd(r000, r001);

    initial += _mm512_reduce_add_pd(r000) ;
    

    len -= 4 * 8 ;
    src += 4 * 8  ;
} 
// while

The stdx::native_simd allows the use of templates for other datatypes.

template<typename T>
using vector_t = std::experimental::native_simd<T>;



while( len >= 8 * sz ) {
    vector_t<T> r00, r01, r02, r03, r04, r05, r06, r07 ;
    r00.copy_from(&src[0 * sz], stdx::vector_aligned) ;
    r01.copy_from(&src[1 * sz], stdx::vector_aligned) ;
    r02.copy_from(&src[2 * sz], stdx::vector_aligned) ;
    r03.copy_from(&src[3 * sz], stdx::vector_aligned) ;
    r04.copy_from(&src[4 * sz], stdx::vector_aligned) ;
    r05.copy_from(&src[5 * sz], stdx::vector_aligned) ;
    r06.copy_from(&src[6 * sz], stdx::vector_aligned) ;
    r07.copy_from(&src[7 * sz], stdx::vector_aligned) ;
    
    r00 += r04 ;
    r01 += r05 ;
    r02 += r06 ;
    r03 += r07 ;
    
    r00 += r02 ;
    r01 += r03 ;
    
    r00 += r01 ;

    initial += stdx::reduce(r00) ;

    len -= 8 * sz ;
    src += 8 * sz ;
} // while

while( len >= 4 * sz ) {
    vector_t<T> r00, r01, r02, r03 ;
    r00.copy_from(&src[0 * sz], stdx::vector_aligned) ;
    r01.copy_from(&src[1 * sz], stdx::vector_aligned) ;
    r02.copy_from(&src[2 * sz], stdx::vector_aligned) ;
    r03.copy_from(&src[3 * sz], stdx::vector_aligned) ;
    
    r00 += r02 ;
    r01 += r03 ;
    
    r00 += r01 ;

    initial += stdx::reduce(r00) ;

    len -= 4 * sz ;
    src += 4 * sz ;
} // while

There's a third approach that uses a recursive C++ template expressing the reduction algorithm. Suprisingly this formed as well as the intrinsic implementation and templated simd, where the trivial loop did not.

template<typename T>
inline static vector_t<T> reduce(vector_t<T> a, T *srcB) 
// terminal case for recursion
{
    vector_t<T> b ;
    b.copy_from(srcB, stdx::
vector_aligned
);
    return a + b ;
}

inline static auto reduce(auto a, auto srcB, auto... args) 
// consume argument and recurse
{
    return reduce(reduce(a, srcB), args...) ;
}

vinitial = 0 ;
while( len >= 8 * sz ) {
    vinitial += reduce(vector_t<T>(0), &src[0 * sz], &src[1 * sz], &src[2 * sz], &src[3 * sz], &src[4 * sz], &src[5 * sz], &src[6 * sz], &src[7 * sz]) ;
    len -= 8 * sz ;
    src += 8 * sz ;
} 
// while

initial += stdx::reduce(vinitial) ;
/*
 *
 */
vinitial = 0 ;
while( len >= 4 * sz ) {
    vinitial += reduce(vector_t<T>(0), &src[0 * sz], &src[1 * sz], &src[2 * sz], &src[3 * sz]) ;
    len -= 4 * sz ;
    src += 4 * sz ;
} 
// while

initial += stdx::reduce(vinitial) ;

r/intel • • 6d ago

Review Intel Core i9-14900KS with fine-tuning to take on AMD X3D

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pcgameshardware.de
122 Upvotes

r/intel • • 7d ago

Information 22 hrs of battery life: Intel Panther Lake makes powerful Windows laptops efficient

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notebookcheck.net
116 Upvotes

r/intel • • 7d ago

News This ASRock's Diamond Rapids motherboard fits 4TB of DDR5 on an E-ATX-sized board

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videocardz.com
34 Upvotes

r/intel • • 7d ago

Rumor / Leak Intel Razor Lake-S reportedly targets 2028 launch, keeping LGA 1954 socket

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videocardz.com
39 Upvotes

r/intel • • 7d ago

Rumor / Leak Intel Razor Lake-S Reportedly Due in 2028 on LGA-1954

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techpowerup.com
130 Upvotes

r/intel • • 8d ago

News Maxsun updates Panther Lake and Wildcat Lake NAS motherboards with 10GbE and up to 128GB DDR5

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videocardz.com
44 Upvotes

r/intel • • 9d ago

Discussion Why Intel Couldn't kill AMD

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youtube.com
0 Upvotes

r/intel • • 9d ago

Review Intel’s Fastest iGPU Yet! Core Ultra X9 388H + 9600 MT/s RAM Tested

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youtube.com
53 Upvotes

r/intel • • 9d ago

News MSI introduces Cubi mini PC with Intel Wildcat Lake processors, promises tool-free maintenance

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videocardz.com
22 Upvotes

r/intel • • 10d ago

Rumor / Leak Intel Core Ultra 4000 Nova Lake-H processor has been pictured, featuring 16 core design

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videocardz.com
86 Upvotes

r/intel • • 10d ago

News CPU-Z 3.02 adds support for Intel Razor Lake, successor to Nova Lake

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videocardz.com
50 Upvotes

r/intel • • 10d ago

Rumor / Leak Intel Core Ultra 4000 desktop “Nova Lake-S” CPUs will reportedly limit frequency to 5.1 GHz above 90°C

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videocardz.com
120 Upvotes

r/intel • • 11d ago

News What Is the Intel 14A PDK 0.9, and Why Does It Matter to Foundry Customers?

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intel.com
42 Upvotes

r/intel • • 11d ago

News The Performance Behind the Scares: Why 1% Lows Matter

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game.intel.com
69 Upvotes

r/intel • • 12d ago

News Intel to end standard orders for Core Ultra 200H and 200U processors in May 2027

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videocardz.com
48 Upvotes